1. Field of the Invention
The present invention is related to the field of data storage in a processor. In particular, the present invention is related to a multi-ported register file.
2. Description of the Related Art
Microprocessors utilize multi-ported register files to execute micro-operations. Therefore, to speed up the processing of data, the multi-ported register files typically have single-cycle latencies during read and write operations. To meet the high performance, high-density demand, two-stage local and global bit-line architecture is employed. FIG. 1 illustrates a conventional multi-ported register file. As illustrated in FIG. 1, a conventional multi-ported register file comprises an m-row×n-column array of register file cells with multiple read/write ports. Although, FIG. 1 illustrates a single read port comprising a 256-row×32-column array of register file cells (array), one having ordinary skill in the art will appreciate that multiple read/write ports may be used. The 256 rows of register file cells in the array are grouped into 8 banks of register file cells comprising 32 rows each. Each register file cell 105 in the array stores a binary bit, and is identical in construction to other register file cells in the array. Each register file cell 105 comprises at least a pair of pull-down transistors. The pull-down transistors of a register file cell 105 may comprise n-channel metal oxide semiconductor field effect transistors (n-MOS transistors) that are identical in construction to pull-down transistors in other cells in the array. Each register file cell in a row of the array is driven by a word-line (WL). A keeper (not shown) maintains the charge on each LBL after the LBL is pre-charged. In the first column of the array, two LBLs (e.g., LBL0 and LBL1) in each bank are merged via a NAND gate 110 and the output of the NAND gate is coupled to at least a pull-down transistor 120. Each LBL couples 16 register file cells in the column to the NAND gate. Each NAND gate in a bank of register file cells is identical in construction to other NAND gates in the array. So also, each pull-down transistor coupled to the output of the NAND gate in a bank of register file cells is identical in construction to other pull-down transistors coupled to the outputs of the NAND gates in the array. As illustrated in the first column of the array of register file cells, a global bit-line (e.g., GBL0) couples at least the pull-down transistor 120 to a data output line D0 via an inverter 140.
Data in register file cells is available at the data output lines D0–D31 by pre-charging a bank and activating a row in the bank using a word-line. Due to the large size of a register file (i.e., the large number of rows) a significant unwanted delay is experienced in accessing data from register file cells that are furthest away from the data output lines D0–D31. For example, data in register file cells in the first row of the array activated by WL0, take longer to reach data output lines D0–D31 (due to at least gate delays and the RC time constant of the traces) than data in register file cells in row 256.
Increasing the strength (i.e., increasing the drive current) of the pull-down transistors of the register file cells to decrease the read delay causes noise immunities of the data read from the register file cells to degrade. This corrupts the data read out of the register file cells due to unacceptable leakage currents of the pull-down transistors comprising the register file cells. Compensating for the leakage currents by increasing the keeper size is not a viable solution as the time to read the data in the register file cell is increased. Also, increasing the number of LBLs by decreasing the number of register file cells coupled to each LBL is not a viable solution as this increases the global multiplexing delay.